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cy8c21123, cy8c21223, cy8c21323 psoc ? programmable system-on-chip? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-12022 rev. *u revised june 19, 2012 psoc ? programmable system-on-chip ? features powerful harvard-architecture processor: ? m8c processor speeds up to 24 mhz ? low power at high speed ? operating voltage: 2.4 v to 5.25 v ? operating voltages down to 1. 0 v using on-chip switch mode pump (smp) ? industrial temperature range: ?40 c to +85 c advanced peripherals (psoc ? blocks): ? four analog type ?e? psoc blocks provide: ? two comparators with digital to analog converter (dac) references ? single or dual 10-bit 8-to-1 analog to digital converter (adc) ? four digital psoc blocks provide: ? 8- to 32-bit timers and count ers, 8- and 16-bit pulse-width modulators (pwms) ? crc and prs modules ? full duplex uart, spi ? master or slave: connectable to all general-purpose i/o (gpio) pins ? complex peripherals by combining blocks flexible on-chip memory: ? 4 kb flash program storage 50,000 erase/write cycles ? 256 bytes sram data storage ? in-system serial programming (issp) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash complete development tools: ? free development software (psoc designer ? ) ? full-featured, in-circuit em ulator (ice) and programmer ? full-speed emulation ? complex breakpoint structure ? 128-kb trace memory precision, programmable clocking: ? internal 2.5% 24- / 48-mhz main oscillator ? internal low-speed, low-power oscillator for watchdog and sleep functionality programmable pin configurations: ? 25-ma sink, 10-ma source on all gpios ? pull-up, pull-down, high z, strong, or open-drain drive modes on all gpios ? up to eight analog inputs on all gpios ? configurable interrupt on all gpios additional system resources: ? i 2 c master, slave and multi-master to 400 khz ? watchdog and sleep timers ? user-configurable low-voltage detection (lvd) ? integrated supervisory circuit ? on-chip precision voltage reference logic block diagram digital system sram system bus inter r upt controller sleep and watchdog clock sources (includes imo and ilo) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flas h i2c internal voltage ref . digital cloc ks por and lvd system resets system resources analog system analog ref . po r t 1 po r t 0 digital psoc block array analog psoc block array sw itch mode pu mp
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 2 of 44 contents psoc functional overview.............................................. 3 psoc core .................................................................. 3 digital system ............................................................. 3 analog system ............................................................ 4 additional system resources . .................................... 4 psoc device characteristics .. .................................... 5 getting started.................................................................. 5 application notes ........................................................ 5 development kits ........................................................ 5 training ....................................................................... 5 cypros consultants .................................................... 5 solutions library.......................................................... 5 technical support ....................................................... 5 development tool selection ........................................... 6 software ...................................................................... 6 designing with psoc designer ....................................... 7 select components ..................................................... 7 configure components .............. .............. .............. ..... 7 organize and connect ............... .............. .............. ..... 7 generate, verify, and debug....................................... 7 pin information ................................................................. 8 8-pin part pinout ....................................................... 8 16-pin part pinout ...................................................... 8 20-pin part pinout .................................................... 10 24-pin part pinout .................................................... 11 register reference......................................................... 12 register conventions ................................................ 12 register mapping tables .......................................... 12 electrical specifications ................................................ 16 absolute maximum ra tings....................................... 16 operating temperature ............................................ 17 dc electrical characteristics..................................... 17 ac electrical characteristics ..................................... 23 packaging information ................................................... 31 packaging dimensions .............................................. 31 thermal impedances ................................................ 35 solder reflow specifications ..................................... 35 ordering information ...................................................... 36 ordering code definitions . ....................................... 36 acronyms ........................................................................ 37 acronyms used ......................................................... 37 reference documents .................................................... 37 document conventions ................................................. 38 units of measure ....................................................... 38 numeric conventions ............ .................................... 38 glossary .......................................................................... 38 document history page ................................................. 43 sales, solutions, and legal information ...................... 44 worldwide sales and design s upport ......... .............. 44 products .................................................................... 44 psoc solutions ......................................................... 44
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 3 of 44 psoc functional overview the psoc family consists of many programmable system-on-chip controller device s. these devices are designed to replace multiple traditional mcu-based system components with a low cost single-chip programmable component. a psoc device includes configurable blocks of analog and digital logic, and programmable interconnect. this architecture allows you to create customized peripheral configurations, to match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts. the psoc architecture, as shown in figure 1 , consists of four main areas: the core, the system resources, the digital system, and the analog system. configurable global bus resources allow the combining of all device resources into a complete custom system. each psoc device includes four digital blocks. depending on the psoc package, up to two analog comparators and up to 16 gpio are also included. the gpio provide access to the global digital and analog interconnects. psoc core the psoc core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and internal main oscillator (imo), and internal low-speed oscillator (ilo). the cpu core, called the m8c, is a powerful processor with speeds up to 24 mhz. the m8c is a four mips 8-bit harvard-architecture microprocessor. system resources provide additional capability, such as digital clocks or i 2 c functionality for implementing an i 2 c master, slave, multimaster, an internal voltage reference that provides an absolute value of 1.3 v to a number of psoc subsystems, an smp that generates normal operating voltages off a single battery cell, and various system resets supported by the m8c. the digital system consists of an array of digital psoc blocks, which can be configured into any number of digital peripherals. the digital blocks can be connected to the gpio th rough a series of global bus that can route any signal to any pin. this frees designs from the constraints of a fixed peripheral controller. the analog system co nsists of four analog psoc blocks, supporting comparators and analog-to-digital conversion up to 10 bits of precision. digital system the digital system consists of four digital psoc blocks. each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16 , 24, and 32-bit peripherals, which are called user modules. digital peripheral configurations include: pwms (8- and 16-bit) pwms with dead band (8- and 16-bit) counters (8- to 32-bit) timers (8- to 32-bit) uart 8-bit with select able parity (up to two) spi master and slave i 2 c slave, master, multi-master (one available as a system resource) cyclical redundancy checker/generator (8-bit) irda (up to two) pseudo random sequence generators (8- to 32-bit) the digital blocks can be conne cted to any gpio through a series of global bus that can route any signal to any pin. the busses also allow for signal multiplexing and performing logic operations. this configurability frees your designs from the constraints of a fixed peripheral controller. digital blocks are provided in rows of four, where the number of blocks varies by psoc device fam ily. this provi des an optimum choice of system resources for your application. family resources are shown in table 1 on page 5 . figure 1. digital system block diagram digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 ro w 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 1 port 0
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 4 of 44 analog system the analog system consists of f our configurable blocks to allow creation of complex analog signal flows. analog peripherals are very flexible and may be customized to support specific application requirements. some of the more common psoc analog functions (most available as user modules) are: analog-to-digital converters (singl e or dual, with 8-bit or 10-bit resolution) pin-to-pin comparators (one) single-ended comparators (up to 2) with absolute (1.3 v) reference or 8-bit dac reference 1.3 v reference (as a system resource) in most psoc devices, analog blocks are provided in columns of three, which includes one ct (continuous time) and two sc (switched capacitor) blocks. th e cy8c21x23 devices provide limited functionality type ?e? analog blocks. each column contains one ct block and one sc block. the number of blocks on the de vice family is listed in table 1 on page 5 . figure 2. cy8c21x23 anal og system block diagram additional system resources system resources, some of which listed in the previous sections, provide additional capability useful to comp lete systems. additional resources include a switch mode pump, low voltage detection, and power on reset. the merits of each system resource are. digital clock dividers provide three customizable clock frequencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks can be generated using digital psoc blocks as clock dividers. the i 2 c module provides 100 and 400 khz communication over two wires. slave, master, and multi-master modes are all supported. lvd interrupts can signal the application of falling voltage levels, while the advanced por (power on reset) circuit eliminates the need for a system supervisor. an internal 1.3 v voltage reference provides an absolute reference for the analog system, including adcs and dacs. an integrated switch mode pump (smp) generates normal operating voltages from a single 1.2 v battery cell, providing a low cost boost converter. ac ol 1m u x ace00 ace01 array array input configuration aci0[1:0] aci1[1:0] ase10 ase11
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 5 of 44 psoc device characteristics depending on your psoc device characterist ics, the digital and analog systems can have 16, 8, or 4 digital blocks, and 12, 6, o r 4 analog blocks. ta b l e 1 lists the resources available for specific psoc device groups. the psoc device covered by this datasheet is highlighted. getting started the quickest way to understand psoc silicon is to read this datasheet and then use the psoc designer integrated devel- opment environment (ide). this da tasheet is an overview of the psoc integrated circuit and present s specific pin, register, and electrical specifications. for in depth information, along with detailed programming details, see the technical reference manual for this psoc device. for up to date ordering, packaging , and electrical specification information, see the latest ps oc device datasheets on the web at http://www.cypress.com . application notes application notes are an excellent introduction to the wide variety of possible psoc designs. they can be found at http://www.cypress.com . development kits psoc development kits are available online from cypress at http://www.cypress.com and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free psoc technical training (on demand, webinars, and workshops) is available online at http://www.cypress.com . the training covers a wide variety of topics and skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to http://www.cypress.com and refer to cypros consultants. solutions library visit our growing library of solution focused designs at http://www.cypress.com . here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. technical support for assistance with technical issues, search knowledgebase articles and forums at http://www.cypress.com . if you cannot find an answer to your question, call technical support at 1-800-541-4736. table 1. psoc device characteristics psoc part number digital i/o digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size cy8c29x66 up to 64 4 16 up to 12 4 4 12 2 k 32 k cy8c28xxx up to 44 up to 3 up to 12 up to 44 up to 4 up to 6 up to 12 + 4 [1] 1 k 16 k cy8c27x43 up to 44 2 8 up to 12 4 4 12 256 16 k cy8c24x94 up to 56 1 4 up to 48 2 2 6 1 k 16 k cy8c24x23a up to 24 1 4 up to 12 2 2 6 256 4 k cy8c23x33 up to 26 1 4 up to 12 2 2 4 256 8 k cy8c22x45 up to 38 2 8 up to 38 0 4 6 [1] 1 k 16 k cy8c21x45 up to 24 1 4 up to 24 0 4 6 [1] 512 8 k cy8c21x34 up to 28 1 4 up to 28 0 2 4 [1] 512 8 k cy8c21x23 up to 16 1 4 up to 8 0 2 4 [1] 256 4 k cy8c20x34 up to 28 0 0 up to 28 0 0 3 [1,2] 512 8 k cy8c20xx6 up to 36 0 0 up to 36 0 0 3 [1,2] up to 2 k up to 32 k notes 1. limited analog functionality. 2. two analog blocks and one capsense ? .
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 6 of 44 development tool selection software psoc designer at the core of the psoc development software suite is psoc designer. utilized by thousan ds of psoc developers, this robust software has been facilitating psoc designs for years. psoc designer is available free of charge at http://www.cypress.com. psoc designer comes with a free c compiler. psoc designer software subsystems you choose a base device to work with and then select different onboard analog and digital components called user modules that use the psoc blocks. examples of user modules are adcs, dacs, amplifiers, and filters. you configure the user modules for your chosen application and connect them to each other and to the proper pins. then you generate your project. this prepop- ulates your project with apis and libraries that you can use to program your application. the tool also supports easy development of multiple configura- tions and dynamic reconfigurat ion. dynamic reconfiguration allows for changing configurations at run time. code generation tools psoc designer supports multiple third-party c compilers and assemblers. the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. the choice is yours. assemblers. the assemblers allow assembly code to be merged seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers. c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs for the psoc family devices. the optimizing c compilers provide all the features of c tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow the designer to read and program and read and write data memory, read and write i/o registers, read and write cpu registers, set and clear break- points, and provide program run, halt, and step control. the debugger also allows the designer to create a trace buffer of registers and memory lo cations of interest. in-circuit emulator a low cost, high functionality in -circuit emulator (ice) is available for development support. this hardware has the capability to program single device s. the emulator consists of a base unit that connects to the pc by way of a usb port. the base unit is universal and operates with all psoc devices. emulation pods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full speed (24mhz) operation. standard cypress psoc ide tools are available for debugging the cy8c20x36a/66a family of parts. however, the additional trace length and a minimal grou nd plane in the flex-pod can create noise problems that make it difficult to debug the design. a custom bonded on-chip debug (ocd) device is available in a 48-pin qfn package. the ocd device is recommended for debugging designs that have high current and/or high analog accuracy requirements. the qfn package is compact and is connected to the ice through a high density connector. psoc programmer flexible enough to be used on the bench in development, yet suitable for factory programming, psoc programmer works either as a standalone programming application or it can operate directly from psoc designer. psoc programmer software is compatible with both psoc ice-cube in-circuit emulator and psoc miniprog. psoc programmer is available free of charge at http://www.cypress.co m/psocprogrammer.
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 7 of 44 designing with psoc designer the development process for the psoc device differs from that of a traditional fixed function mi croprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variet y of user-selectable functions. the psoc development process can be summarized in the following four steps: 1. select user modules 2. configure user modules 3. organize and connect 4. generate, verify, and debug select components psoc designer provides a library of pre-built, pre-tested hardware peripheral components called "user modules." user modules make selecting and implementing peripheral devices, both analog and digital, simple. configure components each of the user modules you select establishes the basic register settings that implement the selected function. they also provide parameters and properties that allow you to tailor their precise configuration to your part icular application. for example, a pwm user module configures one or more digital psoc blocks, one for each 8 bits of resolu tion. the user module parameters permit you to establish the pulse width and duty cycle. configure the parameters and properties to corre- spond to your chosen application. enter values directly or by selecting values from drop-dow n menus. all the user modules are documented in datasheets that may be viewed directly in psoc designer or on the cypress website. these user module datasheets explain the internal operation of the user module and provide performance specifications. each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design. organize and connect you build signal chains at the chip level by interconnecting user modules to each other and the i/o pins. you perform the selection, configuration, and routing so that you have complete control over all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, you perform the "generate configuration files" step. this causes psoc designer to generate source code that automatic ally configures the device to your specification and provides the software for the system. the generated code provides application programming interfaces (apis) with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. a complete code development environment allows you to develop and customize your applications in c, assembly language, or both. the last step in the development process takes place inside psoc designer's debugger (access by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full speed. psoc designer debugging capabil- ities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface prov ides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 8 of 44 pin information this section describes, lists, and illustrates the cy8c21x23 pso c device pins and pinout confi gurations. every port pin (labele d with a ?p?) is capable of digital i/o. however, v ss , v dd , smp, and xres are not capable of digital i/o. 8-pin part pinout 16-pin part pinout table 2. pin definition s ? cy8c21123 8-pin soic pin no. type pin name description figure 3. cy8c21123 8-pin soic digital analog 1 i/o i p0[5] analog column mux input 2 i/o i p0[3] analog column mux input 3 i/o p1[1] i 2 c serial clock (scl), issp-sclk [3] 4 power v ss ground connection 5 i/o p1[0] i 2 c serial data (sda), issp-sdata [3] 6 i/o i p0[2] analog column mux input 7 i/o i p0[4] analog column mux input 8 power v dd supply voltage legend : a = analog, i = input, and o = output. soic 1 2 3 4 8 7 6 5 v dd p0[4], a, i p0[2], a, i p1[0], i2c sda a, i, p0[5] a, i, p0[3] i2c scl, p1[1] v ss table 3. pin definition s ? cy8c21223 16-pin soic pin no. type pin name description figure 4. cy8c21223 16-pin soic digital analog 1 i/o i p0[7] analog column mux input 2 i/o i p0[5] analog column mux input 3 i/o i p0[3] analog column mux input 4 i/o i p0[1] analog column mux input 5 power smp smp connection to required external components 6 power v ss ground connection 7 i/o p1[1] i 2 c scl, issp-sclk [3] 8 power v ss ground connection 9 i/o p1[0] i 2 c sda, issp-sdata [3] 10 i/o p1[2] 11 i/o p1[4] optional external clock input (extclk) 12 i/o i p0[0] analog column mux input 13 i/o i p0[2] analog column mux input 14 i/o i p0[4] analog column mux input 15 i/o i p0[6] analog column mux input 16 power v dd supply voltage legend a = analog, i = input, and o = output. soic v dd p0[6], a, i p0[4], a, i p0[2], a, i p0[0], a, i p1[4], extclk p1[2] p1[0], i2c sda 16 15 14 13 12 11 1 2 3 4 5 6 7 8 a, i, p0[7] a, i, p0[5] a, i, p0[3] a, i, p0[1] smp v ss i2c scl, p1[1] v ss 10 9
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 9 of 44 table 4. pin definitions ? cy8c 21223 16-pin qfn with no e-pad [3] pin no. type pin name description figure 5. cy8c21223 16-pin qfn digital analog 1 i/o i p0[3] analog column mux input 2 i/o i p0[1] analog column mux input 3 i/o p1[7] i 2 c scl 4 i/o p1[5] i 2 c sda 5 i/o p1[3] 6 i/o p1[1] i 2 c scl, issp-sclk [3] 7 power v ss ground connection 8 i/o p1[0] i 2 c sda, issp-sdata [3] 9 i/o p1[6] 10 i/o p1[4] extclk 11 input xres active high external reset with internal pull-down 12 i/o i p0[4] v ref 13 power v dd supply voltage 14 i/o i p0[7] analog column mux input 15 i/o i p0[5] analog column mux input 16 nc no connection. pin must be left floating legend a = analog, i = input, and o = output. qfn ( top view ) 1 2 3 4 12 11 10 9 5 6 7 8 13 14 15 16 p0[4], v ref p0[5], ai p0[7], ai v dd p1[3] i2c scl, p1[1] v ss i2c sda, p1[0] xres p1[4] p1[6] ai, p0[3] ai, p0[1] i2c scl, p1[7] i2c sda, p1[5] nc notes 3. these are the issp pins, which are not high z at por (power on reset). see the psoc technical reference manual for details. 4. the center pad on the qfn package must be connected to gr ound (vss) for best mechanical, t hermal, and electrical performance. if not connected to ground, it must be electrically floated and not connected to any other signal.
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 10 of 44 20-pin part pinout table 5. pin definition s ? cy8c21323 20-pin ssop pin no. type pin name description figure 6. cy8c21323 20-pin ssop digital analog 1 i/o i p0[7] analog column mux input 2 i/o i p0[5] analog column mux input 3 i/o i p0[3] analog column mux input 4 i/o i p0[1] analog column mux input 5 power v ss ground connection 6 i/o p1[7] i 2 c scl 7 i/o p1[5] i 2 c sda 8 i/o p1[3] 9 i/o p1[1] i 2 c scl, issp-sclk [3] 10 power v ss ground connection 11 i/o p1[0] i 2 c sda, issp-sdata [3] 12 i/o p1[2] 13 i/o p1[4] optional extclk input 14 i/o p1[6] 15 input xres active high external reset with internal pull-down 16 i/o i p0[0] analog column mux input 17 i/o i p0[2] analog column mux input 18 i/o i p0[4] analog column mux input 19 i/o i p0[6] analog column mux input 20 power v dd supply voltage legend a = analog, i = input, and o = output. ssop v dd p0[6], a, i p0[4], a, i p0[2], a, i p0[0], a, i xres p1[6] p1[4], extclk p1[2] p1[0], i2c sda 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 a, i, p0[7] a, i, p0[5] a, i, p0[3] a, i, p0[1] i2c scl, p1[7] i2c sda, p1[5] p1[3] i2c scl, p1[1] v ss v ss
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 11 of 44 24-pin part pinout table 6. pin definition s ? cy8c21323 24-pin qfn [5] pin no. type pin name description figure 7. cy8c21323 24-pin qfn digital analog 1 i/o i p0[1] analog column mux input 2 power smp smp connection to required external components 3 power v ss ground connection 4 i/o p1[7] i 2 c scl 5 i/o p1[5] i 2 c sda 6 i/o p1[3] 7 i/o p1[1] i 2 c scl, issp-sclk [3] 8 nc no connection. pin must be left floating 9 power v ss ground connection 10 i/o p1[0] i 2 c sda, issp-sdata [3] 11 i/o p1[2] 12 i/o p1[4] optional (extclk) input 13 i/o p1[6] 14 input xres active high external reset with internal pull-down 15 nc no connection. pin must be left floating 16 i/o i p0[0] analog column mux input 17 i/o i p0[2] analog column mux input 18 i/o i p0[4] analog column mux input 19 i/o i p0[6] analog column mux input 20 power v dd supply voltage 21 power v ss ground connection 22 i/o i p0[7] analog column mux input 23 i/o i p0[5] analog column mux input 24 i/o i p0[3] analog column mux input legend a = analog, i = input, and o = output. qfn (top view) a, i, p0[1] smp v ss i2c scl, p1[7] i2c sda, p1[5] p1[3] 1 2 3 4 5 6 18 17 16 15 14 13 p0[4], a, i p0[2], a, i nc xres p1[6] 24 23 22 21 20 19 p0[3], a, i p0[5], a, i p0[7], a, i v ss v dd p0[6], a, i 7 8 9 10 11 12 i2c scl, p1[1] nc v ss i2c sda, p1[0] p1[2] extclk, p1[4] p0[0], a, i note 5. the center pad on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated and not connected to any other signal.
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 12 of 44 register reference this section lists the registers of the cy8c21x23 psoc device. for detailed register information, refer the psoc technical reference manual . register conventions the register conventions specific to this section are listed in the following table. register mapping tables the psoc device has a total register address space of 512 bytes. the register space is referred to as i/o space and is divided into two banks. the xoi bit in the flag register (cpu_f) determines the bank you are currently in. when the xoi bit is set, you are in bank 1. note in the following register mapping tables, blank fields are reserved and must not be accessed. table 7. register conventions convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 13 of 44 table 8. register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 ase10cr0 80 rw c0 prt0ie 01 rw 41 81 c1 prt0gs 02 rw 42 82 c2 prt0dm2 03 rw 43 83 c3 prt1dr 04 rw 44 ase11cr0 84 rw c4 prt1ie 05 rw 45 85 c5 prt1gs 06 rw 46 86 c6 prt1dm2 07 rw 47 87 c7 08 48 88 c8 09 49 89 c9 0a 4a 8a ca 0b 4b 8b cb 0c 4c 8c cc 0d 4d 8d cd 0e 4e 8e ce 0f 4f 8f cf 10 50 90 d0 11 51 91 d1 12 52 92 d2 13 53 93 d3 14 54 94 d4 15 55 95 d5 16 56 96 i2c_cfg d6 rw 17 57 97 i2c_scr d7 # 18 58 98 i2c_dr d8 rw 19 59 99 i2c_mscr d9 # 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c dc 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk3 de rw 1f 5f 9f df dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w 61 a1 int_msk1 e1 rw dbb00dr2 22 rw pwm_cr 62 rw a2 int_vc e2 rc dbb00cr0 23 # 63 a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 e4 dbb01dr1 25 w 65 a5 e5 dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # adc0_cr 68 # a8 e8 dcb02dr1 29 w adc1_cr 69 # a9 e9 dcb02dr2 2a rw 6a aa ea dcb02cr0 2b # 6b ab eb dcb03dr0 2c # tmp_dr0 6c rw ac ec dcb03dr1 2d w tmp_dr1 6d rw ad ed dcb03dr2 2e rw tmp_dr2 6e rw ae ee dcb03cr0 2f # tmp_dr3 6f rw af ef blank fields are reserved and must not be accessed. # access is bit specific.
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 14 of 44 30 70 rdi0ri b0 rw f0 31 71 rdi0syn b1 rw f1 32 ace00cr1 72 rw rdi0is b2 rw f2 33 ace00cr2 73 rw rdi0lt0 b3 rw f3 34 74 rdi0lt1 b4 rw f4 35 75 rdi0ro0 b5 rw f5 36 ace01cr1 76 rw rdi0ro1 b6 rw f6 37 ace01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd fd 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # table 9. register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw 40 ase10cr0 80 rw c0 prt0dm1 01 rw 41 81 c1 prt0ic0 02 rw 42 82 c2 prt0ic1 03 rw 43 83 c3 prt1dm0 04 rw 44 ase11cr0 84 rw c4 prt1dm1 05 rw 45 85 c5 prt1ic0 06 rw 46 86 c6 prt1ic1 07 rw 47 87 c7 08 48 88 c8 09 49 89 c9 0a 4a 8a ca 0b 4b 8b cb 0c 4c 8c cc 0d 4d 8d cd 0e 4e 8e ce 0f 4f 8f cf 10 50 90 gdi_o_in d0 rw 11 51 91 gdi_e_in d1 rw 12 52 92 gdi_o_ou d2 rw 13 53 93 gdi_e_ou d3 rw 14 54 94 d4 15 55 95 d5 16 56 96 d6 17 57 97 d7 18 58 98 d8 19 59 99 d9 1a 5a 9a da 1b 5b 9b db blank fields are reserved and must not be accessed. # access is bit specific. table 8. register map bank 0 table: user space (continued) name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access blank fields are reserved and must not be accessed. # access is bit specific.
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 15 of 44 1c 5c 9c dc 1d 5d 9d osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw cmp_go_en 64 rw a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 adc0_tr e5 rw dbb01ou 26 rw amd_cr1 66 rw a6 adc1_tr e6 rw 27 alt_cr0 67 rw a7 e7 dcb02fn 28 rw 68 a8 imo_tr e8 w dcb02in 29 rw 69 a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b clk_cr3 6b rw ab eco_tr eb w dcb03fn 2c rw tmp_dr0 6c rw ac ec dcb03in 2d rw tmp_dr1 6d rw ad ed dcb03ou 2e rw tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef 30 70 rdi0ri b0 rw f0 31 71 rdi0syn b1 rw f1 32 ace00cr1 72 rw rdi0is b2 rw f2 33 ace00cr2 73 rw rdi0lt0 b3 rw f3 34 74 rdi0lt1 b4 rw f4 35 75 rdi0ro0 b5 rw f5 36 ace01cr1 76 rw rdi0ro1 b6 rw f6 37 ace01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fls_pr1 fa rw 3b 7b bb fb 3c 7c bc fc 3d 7d bd fd 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # table 9. register map bank 1 table: configuration space (continued) name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access blank fields are reserved and must not be accessed. # access is bit specific.
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 16 of 44 electrical specifications this section presents the dc and ac electric al specifications of the cy8c21x23 psoc de vice. for up to date electrical specifica tions, check if you have the latest datas heet by visiting the web at http://www.cypress.com . specifications are valid for ?40 c ? t a ? 85 c and t j ? 100 c, except where noted. refer to table 24 on page 25 for the electrical specifications on the imo using slimo mode. absolute maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage 5.25 4.75 3.00 93 khz 12 mhz 24 mhz imo frequency vdd voltage 3.60 6 mhz slimo mode = 0 slimo mode=0 2.40 slimo mode=1 slimo mode=1 slimo mode=1 2.40 3 mhz v a l i d o p e r a t i n g r e g i o n slimo mode=1 slimo mode=0 figure 10. voltage versus cpu frequency figure 11. voltage versus imo frequency table 10. absolute maximum ratings symbol description min typ max units notes t stg storage temperature ?55 ? +100 c higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c. extended duration storage temperatures higher than 65 c degrade reliability. t baketemp bake temperature ? 125 see package label c t baketime bake time see package label ? 72 hours t a ambient temperature with power applied ?40 ? +85 c v dd supply voltage on v dd relative to v ss ?0.5 ? +6.0 v v io dc input voltage v ss ? 0.5 ? v dd + 0.5 v v ioz dc voltage applied to tristate v ss ? 0.5 ? v dd + 0.5 v i mio maximum current into any port pin ?25 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd lu latch-up current ? ? 200 ma
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 17 of 44 operating temperature dc electrical characteristics dc chip-level specifications ta b l e 1 2 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 11. operating temperature symbol description min typ max units notes t a ambient temperature ?40 ? +85 c t j junction temperature ?40 ? +100 c the temperature rise from ambient to junction is package specific. see table 36 on page 35 . you must limit the power consumption to comply with this requirement. table 12. dc chip-level specifications symbol description min typ max units notes v dd supply voltage 2.40 ? 5.25 v see dc por and lvd specifications, table 19 on page 21 . i dd supply current, imo = 24 mhz ? 3 4 ma conditions are v dd = 5.0 v, 25 c, cpu = 3 mhz, sysclk doubler disabled. vc1 = 1.5 mhz vc2 = 93.75 khz vc3 = 0.366 khz i dd3 supply current, imo = 6 mhz ? 1.2 2 ma conditions are v dd = 3.3 v, 25 c, cpu = 3 mhz, clock doubler disabled. vc1 = 375 khz vc2 = 23.4 khz vc3 = 0.091 khz i dd27 supply current, imo = 6 mhz ? 1.1 1.5 ma conditions are v dd = 2.55 v, 25 c, cpu = 3 mhz, clock doubler disabled. vc1 = 375 khz vc2 = 23.4 khz vc3 = 0.091 khz i sb27 sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. mid temperature range. ? 2.6 4 a v dd = 2.55 v, 0 c to 40 c i sb sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. ? 2.8 5 a v dd = 3.3 v, ?40 c ?? t a ? 85 c v ref reference voltage (bandgap) 1.28 1.30 1.32 v trimmed for appropriate v dd . v dd = 3.0 v to 5.25 v v ref27 reference voltage (bandgap) 1.16 1.30 1.330 v trimmed for appropriate v dd . v dd = 2.4 v to 3.0 v agnd analog ground v ref ? 0.003 v ref v ref + 0.003 v
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 18 of 44 dc gpio specifications ta b l e 1 3 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. ta b l e 1 4 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 2.4 v to 3.0 v and ?40 c ? t a ? 85 c. typical parameters apply to 2.7 v at 25 c and are for design guidance only. table 13. 5-v and 3.3-v dc gpio specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k ? r pd pull-down resistor 4 5.6 8 k ? v oh high output level v dd ? 1.0 ? ? v i oh = 10 ma, v dd = 4.75 to 5.25 v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 80 ma maximum combined i oh budget. v ol low output level ? ? 0.75 v i ol = 25 ma, v dd = 4.75 to 5.25 v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 150 ma maximum combined i ol budget. i oh high level source current 10 ? ? ma v oh = v dd ? 1.0 v, see the limitations of the total current in the note for v oh i ol low level sink current 25 ? ? ma v ol = 0.75 v, see the limitations of the total current in the note for v ol v il input low level ? ? 0.8 v v dd = 3.0 to 5.25 v ih input high level 2.1 ? v v dd = 3.0 to 5.25 v h input hysteresis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. te m p = 2 5 c c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. te m p = 2 5 c table 14. 2.7-v dc gpio specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k ? r pd pull-down resistor 4 5.6 8 k ? v oh high output level v dd ? 0.4 ? ? v i oh = 2.5 ma (6.25 typ), v dd = 2.4 to 3.0 v (16 ma maximum, 50 ma typ combined i oh budget). v ol low output level ? ? 0.75 v i ol = 10 ma, v dd = 2.4 to 3.0 v (90 ma maximum combined i ol budget). i oh high level source current 2.5 ? ? ma v oh = v dd ? 0.4 v, see the limitations of the total current in the note for v oh i ol low level sink current 10 ? ? ma v ol = 0.75 v, see the limitations of the total current in the note for v ol v il input low level ? ? 0.75 v v dd = 2.4 to 3.0 v ih input high level 2.0 ? ? v v dd = 2.4 to 3.0 v h input hysteresis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. te m p = 2 5 c c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. te m p = 2 5 c
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 19 of 44 dc amplifier specifications the following tables list the guaranteed maximum and minimum specif ications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 15. 5-v dc amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 c v cmoa common mode voltage range 0.0 ? v dd ? 1 v g oloa open loop gain 80 ? ? db i soa amplifier supply current ? 10 30 a table 16. 3.3-v dc amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 c v cmoa common mode voltage range 0 ? v dd ? 1 v g oloa open loop gain 80 ? ? db i soa amplifier supply current ? 10 30 a table 17. 2.7v dc amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 c v cmoa common mode voltage range 0 ? v dd ? 1 v g oloa open loop gain 80 ? ? db i soa amplifier supply current ? 10 30 a
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 20 of 44 dc switch mode pump specifications table 18 lists the guaranteed maximum and minimum specifications for the voltage and tem perature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 18. dc switch mode pump (smp) specifications symbol description min typ max units notes v pump5v 5 v output voltage from pump 4.75 5.0 5.25 v configuration of footnote. [6] average, neglecting ripple. smp trip voltage is set to 5.0 v. v pump3v 3.3 v output voltage from pump 3.00 3.25 3.60 v configuration of footnote. [6] average, neglecting ripple. smp trip voltage is set to 3.25 v. v pump2v 2.6 v output voltage from pump 2.45 2.55 2.80 v configuration of footnote. [6] average, neglecting ripple. smp trip voltage is set to 2.55 v. i pump available output current v bat = 1.8 v, v pump = 5.0 v v bat = 1.5 v, v pump = 3.25 v v bat = 1.3 v, v pump = 2.55 v 5 8 8 ? ? ? ? ? ? ma ma ma configuration of footnote. [6] smp trip voltage is set to 5.0 v. smp trip voltage is set to 3.25 v. smp trip voltage is set to 2.55 v. v bat5v input voltage range from battery 1.8 ? 5.0 v configuration of footnote. [6] smp trip voltage is set to 5.0 v. v bat3v input voltage range from battery 1.0 ? 3.3 v configuration of footnote. [6] smp trip voltage is set to 3.25 v. v bat2v input voltage range from battery 1.0 ? 2.8 v configuration of footnote. [6] smp trip voltage is set to 2.55 v. v batstart minimum input voltage from battery to start pump 1.2 ? ? v configuration of footnote. [6] 0 c ? t a ? 100. 1.25 v at t a = ?40 c. ? v pump_line line regulation (over vi range) ? 5 ? %v o configuration of footnote. [6] v o is the ?v dd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 19 on page 21 . ? v pump_load load regulation ? 5 ? %v o configuration of footnote. [6] v o is the ?v dd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 19 on page 21 . ? v pump_ripple output voltage ripple (depends on cap/load) ? 100 ? mvpp configuration of footnote. [6] load is 5 ma. e 3 efficiency 35 50 ? % configuration of footnote. [6] load is 5 ma. smp trip voltage is set to 3.25 v. e 2 efficiency 35 80 ? % for i load = 1 ma, v pump = 2.55 v, v bat = 1.3 v, 10 uh inductor, 1 uf capacitor, and schottky diode. f pump switching frequency ? 1.3 ? mhz dc pump switching duty cycle ? 50 ? % note 6. l 1 = 2 mh inductor, c 1 = 10 mf capacitor, d 1 = schottky diode. refer to figure 12 on page 21 .
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 21 of 44 figure 12. basic switch mode pump circuit dc por and lvd specifications ta b l e 1 9 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 19. dc por and lvd specifications symbol description min typ max units notes v ppor0 v ppor1 v ppor2 v dd value for ppor trip porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 2.36 2.82 4.55 2.40 2.95 4.70 v v v v dd must be greater than or equal to 2.5 v during startup, reset from the xres pin, or reset from watchdog. v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 v dd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.40 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.45 2.92 3.02 3.13 4.48 4.64 4.73 4.81 2.51 [7] 2.99 [8] 3.09 3.20 4.55 4.75 4.83 4.95 v v v v v v v v v pump0 v pump1 v pump2 v pump3 v pump4 v pump5 v pump6 v pump7 v dd value for pump trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.45 2.96 3.03 3.18 4.54 4.62 4.71 4.89 2.55 3.02 3.10 3.25 4.64 4.73 4.82 5.00 2.62 [9] 3.09 3.16 3.32 [10] 4.74 4.83 4.92 5.12 v v v v v v v v battery c1 d1 + psoc t m vdd vss smp v bat v pump l 1 v dd notes 7. always greater than 50 mv above v ppor (porlev = 00) for falling supply. 8. always greater than 50 mv above v ppor (porlev = 01) for falling supply. 9. always greater than 50 mv above v lvd0 . 10. always greater than 50 mv above v lvd3 .
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 22 of 44 dc programming specifications ta b l e 2 0 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. dc i 2 c specifications ta b l e 2 0 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 20. dc programming specifications symbol description min typ max units notes v ddp v dd for programming and erase 4.5 5.0 5.5 v this specification applies to the functional requirements of external programmer tools v ddlv low v dd for verify 2.4 2.5 2.6 v this specification applies to the functional requirements of external programmer tools v ddhv high v dd for verify 5.1 5.2 5.3 v this specification applies to the functional requirements of external programmer tools v ddiwrite supply voltage for flash write operations 2.70 ? 5.25 v this specification applies to this device when it is executing internal flash writes i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.2 ? ? v i ilp input current when applying v ilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull-down resistor i ihp input current when applying v ihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor v olv output low voltage during programming or verify ? ? v ss + 0.75 v v ohv output high voltage during programming or verify v dd ? 1.0 ? v dd v flash enpb flash endurance (per block) 50,000 [11] ? ? ? erase/write cycles per block flash ent flash endurance (total) [12] 1,800,000 0 ? 0 ? 0 ? 0 erase/write cycles flash dr flash data retention 10 ? ? years notes 11. the 50,000 cycle flash endurance per block is guaranteed if th e flash is operating within one voltage range. voltage ranges are 2.4 v to 3.0 v, 3.0 v to 3.6 v, and 4.75 v to 5.25 v. 12. a maximum of 36 50,000 block endurance cycles is allowed. this may be balanced between operations on 36 1 blocks of 50,0 00 maximum cycles each, 36 2 blocks of 25,000 maximum cycles each, or 36 4 blocks of 12,500 maximum cycles each (and so forth to limit the total number of cycles to 36 50,000 and that no single block ever sees more than 50,000 cycles ).for the full industrial range, you must employ a temperature sensor user module (flashtemp) and feed the result to the temperature argument before writing. refer to the application note, design aids ? reading and writing psoc ? flash ? an2015 for more information on flash apis. 13. all gpio meet the dc gpio v il and v ih specifications mentioned in section dc gpio specifications on page 18 . the i 2 c gpio pins also meet the mentioned specs. table 21. dc i 2 c specifications [13] symbol description min typ max units notes v ili2c input low level ? ? 0.3 v dd v 2.4 v ?? v dd ?? 3.6 v ??0.25 v dd v4.75 v ?? v dd ?? 5.25 v v ihi2c input high level 0.7 v dd ? ? v 2.4 v ?? v dd ?? 5.25 v
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 23 of 44 ac electrical characteristics ac chip-level specifications ta b l e 2 2 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 22. 5-v and 3.3-v ac chip-level specifications symbol description min typ max units notes f imo24 imo frequency for 24 mhz 23.4 24 24.6 [14,15] mhz trimmed for 5 v or 3.3 v operation using factory trim values. refer to figure 11 on page 16 . slimo mode = 0. f imo6 imo frequency for 6 mhz 5.5 6 6.5 [14,15] mhz trimmed for 3.3 v operation using factory trim values. see figure 11 on page 16 . slimo mode = 1. f cpu1 cpu frequency (5 v nominal) 0.0937 24 24.6 [14] mhz 12 mhz only for slimo mode = 0. f cpu2 cpu frequency (3.3 v nominal) 0.0937 12 12.3 [15] mhz slimo mode = 0. f blk5 digital psoc block frequency 0 (5 v nominal) 0 48 49.2 [14,16] mhz refer to the section ac digital block specifications on page 26 . f blk33 digital psoc block frequency (3.3 v nominal) 0 24 24.6 [16] mhz f 32k1 ilo frequency 15 32 64 khz f 32k_u ilo untrimmed frequency 5 ? 100 khz after a reset and before the m8c starts to run, the ilo is not trimmed. see the system resets section of the psoc technical reference manual for details on this timing. t xrst external reset pulse width 10 ? ? s dc24m 24 mhz duty cycle 40 50 60 % dc ilo ilo duty cycle 20 50 80 % step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 46.8 48.0 49.2 [14,15] mhz trimmed. using factory trim values. f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz sr power_up power supply slew rate ? ? 250 v/ms v dd slew rate during power-up. t powerup time from end of por to cpu executing code ? 16 100 ms power-up from 0 v. see the system resets section of the psoc technical reference manual . t jit_imo 24-mhz imo cycle-to- cycle jitter (rms) [17] ? 200 700 ps 24-mhz imo long term n cycle-to-cycle jitter (rms) [17] ? 300 900 ps n = 32 24-mhz imo period jitter (rms) [17] ? 100 400 ps notes 14. 4.75 v < v dd < 5.25 v. 15. 3.0 v < v dd < 3.6 v. refer to the application note, adjusting psoc microcontroller trims for dual voltage-range operation ? an2012 for more information on trimming for operation at 3.3 v. 16. see the individual user module datasheets for information on maximum frequencies for user modules. 17. refer to the application note, understanding datasheet jitter specificati ons for cypress timing products ? an5054 for more information on jitter specifications.
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 24 of 44 table 23. 2.7-v ac chip-level specifications symbol description min typ max units notes f imo12 imo frequency for 12 mhz 11.5 12 0 12.7 [18,19] mhz trimmed for 2.7 v operation using factory trim values. see figure 11 on page 16 . slimo mode = 1. f imo6 imo frequency for 6 mhz 5.5 6 6.5 [18,19] mhz trimmed for 2.7 v operation using factory trim values. see figure 11 on page 16 . slimo mode = 1. f cpu1 cpu frequency (2.7 v nominal) 0.093 3 3.15 [18] mhz 24 mhz only for slimo mode = 0. f blk27 digital psoc block frequency (2.7 v nominal) 0 12 12.5 [18,19] mhz refer to the section ac digital block specifications on page 26 . f 32k1 ilo frequency 8 32 96 khz f 32k_u ilo untrimmed frequency 5 ? 100 khz after a reset and before the m8c starts to run, the ilo is not trimmed. see the system resets section of the psoc technical reference manual for details on this timing. t xrst external reset pulse width 10 ? ? s dc ilo ilo duty cycle 20 50 80 % f max maximum frequency of signal on row input or row output ? ? 12.3 mhz sr power_up power supply slew rate ? ? 250 v/ms v dd slew rate during power-up. t powerup time from end of por to cpu executing code ? 16 100 ms power-up from 0 v. see the system resets section of the psoc technical reference manual . t jit_imo 12-mhz imo cycle-to-cycle jitter (rms) [20] ? 400 1000 ps 12-mhz imo long term n cycle-to-cycle jitter (rms) [20] ? 600 1300 ps n = 32 12-mhz imo period jitter (rms) [20] ? 100 500 ps notes 18. 2.4 v < v dd < 3.0 v. 19. refer to the application note adjusting psoc microcontroller trims for dual voltage-range operation ? an2012 for more information on maximum frequency for user modules. 20. refer to the application note, understanding datasheet jitter specifications for cypress timing products ? an5054 for more information on jitter specifications.
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 25 of 44 ac general purpose i/o specifications ta b l e 2 4 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. figure 13. gpio timing diagram ac amplifier specifications the following tables list the guaranteed maximum and minimum specif ications for the voltage and te mperature ranges: 4.75 v to 5 .25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. settling times, slew rates, and gain bandwidth are based on the analog continuous time psoc block. table 24. 5-v and 3.3-v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns v dd = 4.5 v to 5.25 v, 10% to 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns v dd = 4.5 v to 5.25 v, 10% to 90% trises rise time, slow strong mode, cload = 50 pf 10 27 ? ns v dd = 3 v to 5.25 v, 10% to 90% tfalls fall time, slow strong mode, cload = 50 pf 10 22 ? ns v dd = 3 v to 5.25 v, 10% to 90% table 25. 2.7-v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 3 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 6 ? 50 ns v dd = 2.4 v to 3.0 v, 10% to 90% tfallf fall time, normal strong mode, cload = 50 pf 6 ? 50 ns v dd = 2.4 v to 3.0 v, 10% to 90% trises rise time, slow strong mode, cload = 50 pf 18 40 120 ns v dd = 2.4 v to 3.0 v, 10% to 90% tfalls fall time, slow strong mode, cload = 50 pf 18 40 120 ns v dd = 2.4 v to 3.0 v, 10% to 90% table 26. 5-v and 3.3-v ac amplifier specifications symbol description min typ max units t comp1 comparator mode response time, 50 mvpp signal centered on ref ? ? 100 ns t comp2 comparator mode response time, 2.5 v input, 0.5 v overdrive ? ? 300 ns table 27. 2.7-v ac amplifier specifications symbol description min typ max units t comp1 comparator mode response time, 50 mvpp signal centered on ref ? ? 600 ns t comp2 comparator mode response time, 1.5 v input, 0.5 v overdrive ? ? 300 ns tfallf tfalls trisef tri se s 90% 10% gpio pin
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 26 of 44 ac digital block specifications ta b l e 2 8 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 28. 5-v and 3.3-v ac digital block specifications function description min typ max unit notes all functions block input clock frequency v dd ? 4.75 v ? ? 49.2 mhz v dd < 4.75 v ? ? 24.6 mhz timer input clock frequency no capture, v dd ?? 4.75 v ? ? 49.2 mhz no capture, v dd < 4.75 v ? ? 24.6 mhz with capture ? ? 24.6 mhz capture pulse width 50 [21] ??ns counter input clock frequency no enable input, v dd ? 4.75 v ? ? 49.2 mhz no enable input, v dd < 4.75 v ? ? 24.6 mhz with enable input ? ? 24.6 mhz enable input pulse width 50 [21] ??ns dead band kill pulse width asynchronous restart mode 20 ? ? ns synchronous restart mode 50 [21] ??ns disable mode 50 [21] ??ns input clock frequency v dd ? 4.75 v ? ? 49.2 mhz v dd < 4.75 v ? ? 24.6 mhz crcprs (prs mode) input clock frequency v dd ? 4.75 v ? ? 49.2 mhz v dd < 4.75 v ? ? 24.6 mhz crcprs (crc mode) input clock frequency ? ? 24.6 mhz spim input clock frequency ? ? 8.2 mhz the spi serial clock (sclk) frequency is equal to the input clock frequency divided by 2. spis input clock (sclk) frequency ? ? 4.1 mhz the i nput clock is the spi sclk in spis mode. width of ss_negated between transmissions 50 [21] ??ns transmitter input clock frequency the baud rate is equal to the input clock frequency divided by 8. v dd ? 4.75 v, 2 stop bits ? ? 49.2 mhz v dd ? 4.75 v, 1 stop bit ? ? 24.6 mhz v dd < 4.75 v ? ? 24.6 mhz receiver input clock frequency the baud rate is equal to the input clock frequency divided by 8. v dd ? 4.75 v, 2 stop bits ? ? 49.2 mhz v dd ? 4.75 v, 1 stop bit ? ? 24.6 mhz v dd < 4.75 v ? ? 24.6 mhz note 21. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period).
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 27 of 44 table 29. 2.7-v ac digital block specifications function description min typ max units notes all functions block input clock frequency ? ? 12.7 mhz 2.4 v < v dd < 3.0 v. timer capture pulse width 100 [22] ? ? ns input clock frequency, with or without capture ? ? 12.7 mhz counter enable input pulse width 100 ? ? ns input clock frequency, no enable input ? ? 12.7 mhz input clock frequency, enable input ? ? 12.7 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 100 ? ? ns disable mode 100 ? ? ns input clock frequency ? ? 12.7 mhz crcprs (prs mode) input clock frequency ? ? 12.7 mhz crcprs (crc mode) input clock frequency ? ? 12.7 mhz spim input clock frequency ? ? 6.35 mhz the spi serial clock (sclk) frequency is equal to the input clock frequency divided by 2. spis input clock (sclk) frequency ? ? 4.1 mhz width of ss_ negated between transmissions 100 ? ? ns transmitter input clock frequency ? ? 12.7 mhz the baud rate is equal to the input clock frequency divided by 8. receiver input clock frequency ? ? 12.7 mhz the baud rate is equal to the input clock frequency divided by 8. note 22. 100 ns minimum input pulse width is based on the input synchronizers running at 12 mhz (84 ns nominal period).
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 28 of 44 ac external clock specifications the following tables list the guaranteed maximum and minimum specif ications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 30. 5-v ac external clock specifications symbol description min typ max units notes f oscext frequency 0.093 ?24.6mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power-up imo to switch 150 ? ?s table 31. 3.3-v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.093 ? 12.3 mhz maximum cpu frequency is 12 mhz at 3.3 v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.186 ? 24.6 mhz if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider ensures that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power-up imo to switch 150 ? ?s table 32. 2.7-v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.093 ?6.06 0 mhz maximum cpu frequency is 3 mhz at 2.7 v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.186 ? 12.12 mhz if the frequency of the external clock is greater than 3 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider ensures that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 83.4 ? 5300 ns ? low period with cpu clock divide by 1 83.4 ? ?ns ? power-up imo to switch 150 ? ?s
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 29 of 44 ac programming specifications ta b l e 3 3 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, or 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. ac i 2 c specifications ta b l e 3 4 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c, 3.0 v to 3.6 v and ?40 c ? t a ? 85 c, or 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 33. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 10 ? ms t write flash block write time ? 80 ? ms t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 ? v dd ? 3.6. t dsclk2 data out delay from falling edge of sclk ? ? 70 ns 2.4 ? v dd ? 3.0. t eraseall flash erase time (bulk) ? 20 ? ms erase all blocks and protection fields at once. t program_hot flash block erase + flash block write time ? ? 180 [24] ms 0 c ? tj ? 100 c . t program_cold flash block erase + flash block write time ? ? 360 [24] ms ?40 c ? tj ? 0 c . table 34. ac characteristics of the i 2 c sda and scl pins for v cc ? ? 3.0 v symbol description standard mode fast mode units min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ?s t lowi2c low period of the scl clock 4.7 ?1.3 ?s t highi2c high period of the scl clock 4.0 ?0.6 ?s t sustai2c setup time for a repeated start condition 4.7 ?0.6 ?s t hddati2c data hold time 0 ?0 ?s t sudati2c data setup time 0 250 0 ? 0 100 [23] ? 0 ns 0 t sustoi2c setup time for stop condition 4.0 ?0.6 ?s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ?s t spi2c pulse width of spikes are suppressed by the input filter ? ? 0 50 ns notes 23. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t sudat ? 250 ns must then be met. this automatically becomes the case if the device does not stretch the low period of th e scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t sudat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. 24. for the full industrial range, you must employ a temperature sensor user module (flashtemp) and feed the result to the tempe rature argument before writing. refer to the application note, design aids ? reading and writing psoc ? flash ? an2015 for more information on flash apis.
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 30 of 44 figure 14. definition for timing for fast/standard mode on the i 2 c bus table 35. 2.7-v ac characteristics of the i 2 c sda and scl pins (fast mode not supported) symbol description standard mode fast mode units min max min max f scli2c scl clock frequency 0 100 ??khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ? ? ?s t lowi2c low period of the scl clock 4.7 ? ? ?s t highi2c high period of the scl clock 4.0 ? ? ?s t sustai2c setup time for a repeated start condition 4.7 ? ? ?s t hddati2c data hold time 0 ? ? ?s t sudati2c data setup time 250 ? ? ?ns t sustoi2c setup time for stop condition 4.0 ? ? ?s t bufi2c bus free time between a stop and start condition 4.7 ?? ?s t spi2c pulse width of spikes are suppressed by the input filter. ? ???ns i2c_sda i2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 31 of 44 packaging information this section illustrates the packaging sp ecifications for the cy8c21x23 psoc device, along with the thermal impedances for each package and minimum solder reflow peak temperature. important note emulation tools may require a larger ar ea on the target pcb than the chip's footprint. fo r a detailed description of the emulation tools' dimensions, refe r to the emulator pod drawings at http://www.cypress.com . packaging dimensions figure 15. 8-pin (150-mil) soic 51-85066 *e
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 32 of 44 figure 16. 16-pin (150-mil) soic figure 17. 16-pin qfn with no e-pad 51-85068 *d 001-09116 *f
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 33 of 44 figure 18. 20-pin (210-mil) ssop 51-85077 *e
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 34 of 44 figure 19. 24-pin (4 4) qfn important note for information on the preferred dimensions for mounting qfn packages, refer the application note, application notes for surface mount assembly of amkor's microleadframe (mlf) packages available at http://www.amkor.com . note that pinned vias for thermal conduction are not requi red for the low power 24, 32, and 48-pin qfn psoc devices. 51-85203 *c
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 35 of 44 thermal impedances solder reflow specifications ta b l e 3 7 shows the solder reflow temperature limits that must not be exceeded. table 36. thermal impedances per package package typical ? ja [25] 8-pin soic 186 c/w 16-pin soic 125 c/w 16-pin qfn 46 c/w 20-pin ssop 117 c/w 24-pin qfn [26] 40 c/w table 37. solder reflow specifications package maximum peak temperature (t c ) maximum time above t c ? 5 c 8-pin soic 260 c 30 seconds 16-pin soic 260 c 30 seconds 16-pin qfn 260 c 30 seconds 20-pin ssop 260 c 30 seconds 24-pin qfn 260 c 30 seconds notes 25. t j = t a + power ? ja 26. to achieve the thermal impedance specifi ed for the qfn package, refer to "application notes for surface mount assembly of am kor's microleadframe (mlf) packages" available at http://www.amkor.com . 27. higher temperatures may be required based on the solder melting point. typical temperatures for solder are 220+/-5 c with s n-pb or 245+/-5 c with sn-ag-cu paste. refer to the solder manufacturer specifications.
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 36 of 44 ordering information the following table lists the cy8c21x23 psoc device?s key package features and ordering codes. note for die sales information, contact a local cypress sales office or field applications engineer (fae). ordering code definitions table 38. cy8c21x23 psoc device key features and ordering information package ordering code flash (bytes) ram (bytes) switch mode pump temperature range digital psoc blocks analog blocks digital i/o pins analog inputs analog outputs xres pin 8-pin (150-mil) soic CY8C21123-24SXI 4 k 256 no ?40 c to +85 c 4 4 6 4 0 no 8-pin (150-mil) soic (tape and reel) CY8C21123-24SXIt 4 k 256 no ?40 c to +85 c 4 4 6 4 0 no 16-pin (150-mil) soic cy8c21223-24sxi 4 k 256 yes ?40 c to +85 c 4 4 12 8 0 no 16-pin (150-mil) soic (tape and reel) cy8c21223-24sxit 4 k 256 yes ?40 c to +85 c 4 4 12 8 0 no 16-pin (3 3) qfn with no e-pad cy8c21223-24lgxi 4 k 256 no ?40 c to +85 c 441280yes 20-pin (210-mil) ssop cy8c21323-24pvxi 4 k 256 no ?40 c to +85 c 4 4 16 8 0 yes 20-pin (210-mil) ssop (tape and reel) cy8c21323-24pvxit 4 k 256 no ?40 c to +85 c 4 4 16 8 0 yes 24-pin (4 4) qfn cy8c21323-24lfxi 4 k 256 yes ?40 c to +85 c 4 4 16 8 0 yes 24-pin (4 4) qfn (tape and reel) cy8c21323-24lfxit 4 k 256 yes ?40 c to +85 c 4 4 16 8 0 yes cy 8 c 21 xxx-24xx package type: thermal rating: sx = soic pb-free c = commercial pvx = ssop pb-free i = industrial lfx/lgx = qfn pb-free e = extended speed: 24 mhz part number family code technology code: c = cmos marketing code: 8 = cypress psoc company id: cy = cypress
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 37 of 44 acronyms acronyms used ta b l e 3 9 lists the acronyms that are used in this document. reference documents cy8cplc20, cy8cled16p01, cy8c29x66, cy8c27x43, cy8c24 x94, cy8c24x23, cy8c24x23a, cy8c22x13, cy8c21x34, cy8c21x23, cy7c64215, cy7c603xx, cy8cnp1xx, and cywu sb6953 psoc? programmable system-on-chip technical reference manual (trm) (001-14463) design aids ? reading and writing psoc ? flash ? an2015 (001-40459) adjusting psoc ? trims for 3.3 v and 2.7 v operation ? an2012 (001-17397) understanding datasheet jitter specifications for cypress timing products ? an5054 (001-14503) application notes for surface mount assembly of amkor's microleadframe (mlf) packages ? available at http://www.amkor.com . table 39. acronyms used in this datasheet acronym description acronym description ac alternating current pcb printed circuit board adc analog-to-digital converter pga programmable gain amplifier api application programming interface por power on reset cmos complementary metal oxide semiconductor ppor precision power on reset cpu central processing unit prs pseudo-random sequence crc cyclic redundancy check psoc? programmable system-on-chip ct continuous time pwm pulse width modulator dac digital-to-analog converter qfn quad flat no leads dc direct current sc switched capacitor eeprom electrically erasable programmable read-only memory slimo slow imo gpio general purpose i/o smp switch mode pump ice in-circuit emulator soic small-outline integrated circuit ide integrated development environment spi tm serial peripheral interface ilo internal low speed oscillator sram static random access memory imo internal main oscillator srom supervisory read only memory i/o input/output ssop shrink small-outline package irda infrared data association uart universal asynchronous reciever / transmitter issp in-system serial programming usb universal serial bus lvd low voltage detect wdt watchdog timer mcu microcontroller uni t xres external reset mips million instructions per second
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 38 of 44 document conventions units of measure ta b l e 4 0 lists the units of measures. numeric conventions hexadecimal numbers are represented with all letters in uppercase wi th an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pref ix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicated by an ?h? or ?b? are decimals. table 40. units of measure symbol unit of measure symbol unit of measure db decibels mh millihenry c degree celsius h microhenry f microfarad s microsecond pf picofarad ms millisecond khz kilohertz ns nanosecond mhz megahertz ps picosecond rt-hz root hertz v microvolt k ? kilohm mv millivolt ? ohm mvpp millivolts peak-to-peak a microampere v volt ma milliampere w watt na nanoampere mm millimeter pa pikoampere % percent glossary active high 1. a logic signal having its asserted state as the logic 1 state. 2. a logic signal having the logic 1 state as the higher voltage of the two states. analog blocks the basic programmable opamp circuits. these are sc (switched capacitor) and ct (continuous time) blocks. these blocks can be interconnected to provide adcs, dacs, mu lti-pole filters, gain stages, and much more. analog-to-digital (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog (dac) converter performs the reverse operation. application programming interface (api) a series of software routines that comprise an interface between a computer application and lower level services and functions (for exampl e, user modules and libraries). apis serve as building blocks for programmers that create softwa re applications. asynchronous a signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference a stable voltage reference design that matches the positive temperature coefficient of vt with the negative temperat ure coefficient of vbe, to produce a ze ro temperature coefficient (ideally) reference. bandwidth 1. the frequency range of a message or information processing system measured in hertz. 2. the width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specific ally as, for example, full width at half maximum.
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 39 of 44 bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1. a functional unit that performs a single function, such as an oscillator. 2. a functional unit that may be configured to perfo rm one of several functions, such as a digital psoc block or an analog psoc block. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved for io operations, into which data is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. a set of signals performing a common function and carrying similar data. typically represented using vector notation; fo r example, address[7:0]. 3. one or more conductors that serve as a co mmon connection for a group of related devices. clock the device that generates a periodic signal with a fixed frequen cy and duty cycle. a clock is sometimes used to synchroni ze different logic blocks. comparator an electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler a program that translates a high leve l language, such as c, into machine language. configuration space in psoc devices, the register space accessed when the xio bit, in the cpu_f register, is set to ?1?. crystal oscillator an oscillator in whic h the frequency is controlled by a piezoelectric crystal. typically a piezoelectric crystal is less sensitive to ambient te mperature than other circuit components. cyclic redundancy check (crc) a calculation used to detect errors in data co mmunications, typically performed using a linear feedback shift register. similar calculations may be used for a variety of other purposes such as data compression. data bus a bi-directional set of signals used by a comp uter to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. debugger a hardware and software system that allo ws you to analyze the operation of the system under development. a debugger usually allows th e developer to step through the firmware one step at a time, set break points, and analyze memory. dead band a period of time when neither of two or more signals are in their active state or in transition. digital blocks the 8-bit logic blocks that can act as a counter, timer, se rial receiver, serial transmitter, crc generator, pseudo-random number generator, or spi. glossary (continued)
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 40 of 44 digital-to-analog (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the analog- to-digital (adc) converter pe rforms the reverse operation. duty cycle the relations hip of a clock period high time to its low time, expressed as a percent. emulator duplicates (provides an emul ation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset (xres) an active high signal that is driven into the psoc device. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. flash an electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of eproms, pl us in-system erasability. non-volatile means that the data is retained when power is off. flash block the smallest amount of flash rom space that may be programmed at one time and the smallest amount of flash space that may be pr otected. a flash block holds 64 bytes. frequency the number of cycles or events pe r unit of time, for a periodic function. gain the ratio of output current, vo ltage, or power to input current, voltage, or power, respectively. gain is usually expressed in db. i 2 c a two-wire serial computer bus by philips semiconductors (now nxp semiconductors). i2c is an inter-integrated circuit. it is used to connect low-speed peripherals in an embedded system. the original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control el ectronics. i2c uses only two bi-d irectional pins, clock and data, both running at +5v and pulle d high with resistors. the bus operates at 100 kbits/second in standard mode an d 400 kbits/second in fast mode. ice the in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (psoc designer). input/output (i/o) a device that introduces da ta into or extracts data from a system. interrupt a suspension of a process, such as the ex ecution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (isr) a block of code that normal code execution is diverted to when the m8c receives a hardware interrupt. many interrupt sources may each exis t with its own priority and individual isr code block. each isr code block ends with the reti in struction, returning t he device to the point in the program where it left normal program execution. jitter 1. a misplacement of the timing of a transition from its ideal position. a ty pical form of corruption that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequen cy or phase of successive cycles. low-voltage detect (lvd) a circuit that senses v dd and provides an interrupt to the system when v dd falls lower than a selected threshold. m8c an 8-bit harvard-architecture microprocessor. the microprocessor coordinates all activity inside a psoc by interfacing to the fl ash, sram, and register space. glossary (continued)
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 41 of 44 master device a device that controls the timing for da ta exchanges between two devices. or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external in terface. the controlled device is called the slave device . microcontroller an integrated circuit chip that is desi gned primarily for control systems and products. in addition to a cpu, a microcontroller typically includes memory, timing circuits, and io circuitry. the reason for this is to permit the realization of a co ntroller with a minimal quantity of chips, thus achieving maximal possible miniaturization. this in turn, reduces the volume and the cost of the controller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal the reference to a circuit containing both analog and digital techniques and components. modulator a device that imposes a signal on a carrier. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. 2. the random variations of one or mo re characteristics of any entity such as voltage, current, or data. oscillator a circuit that may be crystal controlled and is used to generate a clock frequency. parity a technique for testing transmitting data. typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts the pin number assignment: the relation bet ween the logical inputs and outputs of the psoc device and their physical counterparts in t he printed circuit board (pcb) package. pinouts involve pin numbers as a link between schematic and pcb design (both being computer generated files) and may also involve pin names. port a group of pins, usually eight. power on reset (por) a circuit that forces the psoc device to reset when the voltage is lower than a pre-set level. this is one type of hardware reset. psoc ? cypress semiconductor?s psoc ? is a registered trademark and programmable system-on- chip? is a trademark of cypress. psoc designer? the software for cypress? programmable system-on-chip technology. pulse width modulator (pwm) an output in the form of duty cycle which varies as a function of the applied measurand ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specific capacity, such as a bit or byte. reset a means of bringing a system back to a know state. see hardware reset and software reset. rom an acronym for read only memory. a data-storage device from which data can be read out, but new data cannot be written in. glossary (continued)
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 42 of 44 serial 1. pertaining to a process in which all events occur one after the other. 2. pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift register a memory storage device t hat sequentially shifts a word either left or right to output a stream of serial data. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, th e slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. the controlling device is called the master device. sram an acronym for static random access memory. a memory device where you can store and retrieve data at a high rate of speed. the term static is used because, after a value is loaded into an sram cell, it remains unchanged until it is explicitly al tered or until power is removed from the device. srom an acronym for supervisory read only memory. the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the functions of the srom may be accessed in normal user code, operating from flash. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. a signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. a system whose operation is syn chronized by a clock signal. tri-state a function whose output ca n adopt three states: 0, 1, and z (high-impedance). the function does not drive any value in the z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowin g another output to drive the same net. uart a uart or universal asynchronous receiver-tra nsmitter translates between parallel bits of data and serial bits. user modules pre-build, pre-tested hardw are/firmware peripheral functions that take care of managing and configuring the lower level analog and digital psoc blocks. user modules also provide high level api (application programming interface) for the peripheral function. user space the bank 0 space of the register map. the re gisters in this bank are more likely to be modified during normal program execution and not just durin g initialization. registers in bank 1 are most likely to be modified only during the initialization phase of the program. v dd a name for a power net meaning "voltage drain." the most positive power supply signal. usually 5 v or 3.3 v. v ss a name for a power net meaning "voltage source." the most negative power supply signal. watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of time. glossary (continued)
cy8c21123, cy8c21223, cy8c21323 document number: 38-12022 rev. *u page 43 of 44 document history page document title: cy8c21123, cy8c21223, cy8c21323 psoc ? programmable system-on-chip? document number:38-12022 revision ecn orig. of change submission date description of change ** 133248 nwj see ecn new silicon and document (revision **). *a 208900 nwj see ecn add new part, new package and update all ordering codes to pb-free. *b 212081 nwj see ecn expand and prepare preliminary version. *c 227321 cms team see ecn update specs., data, format. *d 235973 sfv see ecn updated overview and electrical spec. chapters, along with 24-pin pinout. added cmp_go_en register (1,64h) to mapping table. *e 290991 hmt see ecn update datasheet standards per sfv me mo. fix device table. add part numbers to pinouts and fine tune. change 20-pin ssop to cy8c21323. add reflow temp. table. update diagrams and specs. *f 301636 hmt see ecn dc chip-level specification changes. update links to new cy.com portal. *g 324073 hmt see ecn obtained clearer 16 soic package. update thermal impedances and solder reflow tables. re-add pinout issp notatio n. fix adc type-o. fix tmp register names. update electrical specificatio ns. add cy logo. update cy copyright. make datasheet final. *h 2588457 ket/hmi/ aesa 10/22/2008 new package information on page 9. converted datasheet to new template. added 16-pin ofn package diagram. *i 2618175 ogne/pyrs 12/09/08 added note in ordering information section. changed title from psoc mixed-signal array to psoc programmable system-on-chip. updated ?devel- opment tools? and ?designing with psoc designer? sections on pages 5 and 6 *j 2682782 maxk/aesa 04/03/2009 corrected 16 col pinout. *k 2699713 maxk 04/29/09 minor ecn to correct paragraph style of 16 col pinout. no change in content. *l 2762497 jvy 09/11/2009 updated dc gpio, ac chip-level, and ac programming specifications as follows: modified f imo6 and t write specifications. replaced t ramp time) specification with sr power_up (slew rate) specification. added note [11] to flash endurance specification. added i oh , i ol , dc ilo , f 32k_u , t powerup , t eraseall , t program_hot , and t program_cold specifications.. *m 2792630 tto 10/26/2009 updated ordering information fo r cy8c21223-24lgxi to indicate availability of xres pin. *n 2901653 njf 03/30/2010 changed 16-pin col to 16-pin qfn in the datasheet. added contents . updated links in sales, solutions, and legal information updated cypress website links. added t baketemp and t baketime parameters in absolute maximum ratings updated 5-v and 3.3-v ac chip-level specifications updated notes in packaging information and package diagrams. updated ordering code definitions *o 2928895 yji 05/06/2010 no technical updates. included with eros spec. *p 3044869 njf 10/01/2010 added psoc device characteristics table . added dc i 2 c specifications table. added f 32k_u max limit. added tjit_imo specific ation, removed existing jitter specifications. updated units of measure, acronyms, glossary, and references sections. updated solder reflow specifications. no specific changes were made to ac digital block specifications table and i 2 c timing diagram. they were updated for clearer understanding. updated figure 13 since the labelling for y-axis was incorrect. template and styles update. *q 3263669 yji 05/23/2011 updated 16-pin soic and 20-pin ssop package diagrams. updated development tool selection and designing with psoc designer sections.
document number: 38-12022 rev. *u revised june 19, 2012 page 44 of 44 psoc designer is a trademark and psoc is a registered trademark of cypress semiconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed a ssociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. cy8c21123, cy8c21223, cy8c21323 ? cypress semiconductor corporation, 2004-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 *r 3383787 gir 09/26/2011 the text ?pin must be left floating? is included under description of nc pin in table 6 on page 11 . updated table 37 on page 35 for improved clarity. *s 3558729 rjvb 03/22/2012 updated 16-pin soic package. *t 3598261 lure/xzng 04/24/2012 changed the pwm description string from ?8- to 32-bit? to ?8- and 16-bit?. *u 3649990 bvi/yliu 06/19/2012 updated description of nc pin as ?no connection. pin must be left floating? document title: cy8c21123, cy8c21223, cy8c21323 psoc ? programmable system-on-chip? document number:38-12022

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